| STUDENTS
> Computer Architecture I
|
Computer Architecture I
Note:
Whilst every effort is made to keep the syllabus and assessment records correct
for this course, the precise details must be checked with the lecturer(s).
| Code: | 1001 |
| Year: | 1 |
| Prerequisites: | none |
| Term: | 1 |
| Taught By: | Peter Rounce (50%)
Kevin Bryson (50%)
|
| Aims: |
To show how information is represented in a computer. To explain how computers execute instructions to 'process' data. To explain the structure and interconnection of computers and the reasons for this. To show how programs are mapped on to the architecture. To demonstrate the basics of I/O, the role of the interface, and the use of polling, interrupts and DMA. To cover the architectural requirements to provide for secure multi-user, multi-processing systems. Performance issues must pervade the course material, but there is a need to deal with specific architectural features that enhance performance: cache memory, pipelining, superscalar architectures. To establish the role of the operating system in managing resources and providing for multiprocessing. To educate students to understand the design and performance of the most common computer systems from micro-controllers (the commonest) to workstations (the most well-known). |
| Learning Outcomes: |
Students will understand the basic principles behind the design of modern computer systems, and will be able to apply them to novel designs that they may come across in the future - abstraction (from instruction set to assembler programming, from processor and memory and bus hardware up to operating systems and compilers) is a key understanding outcome.
|
Content:
| Computer structure | processor
memory
i/o,
Secondary storage
buses,
clocks,
sequential operation,
, Fetch-Execute cycle. |
| Data representation | Binary and hex integer
representations and conversions.
Fixed-length arithmetic.
2's complement representation.
IEEE FP representation,
Analogue versus digital. |
| Memory organisation | Addresses.
Memory organisation into bytes,
words, longs.
Memory-mapped i/o |
| The processor or CPU | Simple internal structure.
Registers, program counter etc.
The execution cycle. |
| Instructions | The CPU instruction set – syntax and semantics.
Addressing modes.
Encoding and decoding. |
| Data Structures | Stacks, queues and linked links.
The stack and stack frame for supporting parameters, local variables, and recursion. |
| Basic Hardware | Structure and operations of basic hardware devices from transistor to memory devices. |
| Simple I/O | Handling simple devices: : the interface and the peripheral
Device registers and polling
Interrupts and interrupt hardware
interrupt vectors. |
| More complex devices | Programmable devices.
Block-mode devices.
DMA: system structure and operation |
| Magnetic and Optical Storage | Basic bit storage
Tapes and disks: structure and operation of discs
Organisation of disc blocks into
files. |
| Memory management | Paging
page tables
MMUs
Page faults
associative page table caches. |
| Performance enhancements | Pipelining
caches memory
RISC vs CISC architectures
superscalar architectures
VLIW
multi-threaded and trace-based architectures. |
| Micro-controllers | Role: low cost, low power, small size computer systems
I/O systems: analogue and digital |
Method of Instruction:
Lecture presentations, problem classes, lab sessions and
tutorial sessions. There are two pieces of coursework, each worth 7.5% of the total marks for this course.
Assessment:
The course has the following assessment components:
- Written Examination (2.5 hours, 85%)
- Coursework Section (2 pieces, 15%)
To pass this course, students must:
- Obtain an overall pass mark of 40% for all sections combined
The examination rubric is:
Answer 3 questions out of 5. All questions carry equal marks.Resources:
Irv Englander, The Architecture of Computer Hardware and Systems Software : An Information Technology Approach, Wiley, 3rd Edition, ISBN 0-471-07325-3
Lecture notes
Wiley Student Companion Site for Irv Englander
|
+44 (0)20 7679 7214 - Copyright © 1999-2007
UCL
