Links to Evolvable Hardware Pages:
Adrian Thompson at Sussex University was the first to evolve hardware intrinsically, directly evolving the architecture bits in fine-grained FPGAs. He is currently researching how to improve the robustness of the novel architectures he has developed using this method, and has a small group working with him in this exciting area. For more information, see their evolutionary electronics page.
The Evolvable Systems Lab at the Electrotechnical Laboratory in Japan work on intrinsic evolvable hardware and have developed a hardware evolution architecture. They belive that a more symbolically encoded chromosome is the key to improving scalability. They are also currently researching applications for the technique, and have had success with evolving compression and pattern recognition techniques.
Julian Miller has done a lot of work on the extrinsic evolution of combinational digital circuits, covering both evolvability and innovative circuit design.
John Koza, the father of genetic programming (GP), has recently been working on evolution of analogue circuit designs using a GP-like representation with nodes of a tree being circuit elements and circuit-modifying elements. Previously all simulated using SPICE, his tem at Berkley are now looking at intrinsic evolution using real FPGAs.
Hitoshi Hemmi, a researcher at the ATR HIP Lab., has worked on the evolution of hardware designs using a typed GP-style representation of an HDL. Correct syntax was ensured in the initial trees by generating them from the HDL grammar, which he suggested could also be evolved. This is probably the earliest case of a developmental process being used to automatically design hardware.
I use Xilinx Virtex FPGAs to evolve circuits intrinsically. The easiest way to do this is to buy a Virtex development board. The one I use is the Alpha Data ADM-XRC. As this is PCI-based it allows for much faster configuration than serial boards, and its API makes both configuration and data transfer a doddle.
FPGAs are not the only programmable hardware devices. The BRASS group at Berkeley are researching applications of EHW, including a 'Reconfigurable Processor'. Perhaps this could be the first step to efficient fault tolerance for microprocessors?
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