ABSTRACT
Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions
Alberto De Souza
VLIW (Very Long Instruction Word) machines possibly provide the
most direct way to exploit instruction level parallelism; however, they
cannot be used to emulate current general-purpose instruction set archi
tectures. Programs scheduled for a particular implementation of a
VLIW model cannot be guaranteed to be binary compatible with other
implementations of the same machine model with different number of
functional-units.
In this talk we will describe an architecture, named dynamically trace
scheduled VLIW (DTSVLIW), which can be used to implement
machines that execute code of current RISC or CISC instruction set
architectures in a VLIW fashion, with backward code compatibility.
Some preliminary performance measurements of the DTSVLIW,
obtained with an execution-driven simulator running the SPECint95
benchmark suite, will also be presented.
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